Junior ASIC Design Engineer - Astera Labs

Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field. Experience: 0-2 years of experience in logic design (relevant internships, university labs, or hands-on academic projects are highly valued). Technical Skills: Foundational knowledge of Verilog and/or SystemVerilog . Strong understanding of digital design principles and fundamental RTL coding concepts. Foundational knowledge of Verilog and/or SystemVerilog . Strong understanding of digital design principles and fundamental RTL coding concepts. Soft Skills: Excellent communication skills with a strong motivation to learn, adapt, and collaborate effectively within cross-functional teams.

Design Ownership & Implementation Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams Quality Assurance & Design Optimization Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient Apply design techniques to meet PPA (Power, Performance, Area) targets Contribute to design quality through verification and validation activities Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient Apply design techniques to meet PPA (Power, Performance, Area) targets Contribute to design quality through verification and validation activities Methodology Innovation & Collaboration Participate in design methodology improvements and tool automation initiatives Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter Collaborate effectively across teams to ensure seamless integration Participate in design methodology improvements and tool automation initiatives Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter Collaborate effectively across teams to ensure seamless integration

Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field. Experience: 0-2 years of experience in logic design (relevant internships, university labs, or hands-on academic projects are highly valued). Technical Skills: Foundational knowledge of Verilog and/or SystemVerilog . Strong understanding of digital design principles and fundamental RTL coding concepts. Foundational knowledge of Verilog and/or SystemVerilog . Strong understanding of digital design principles and fundamental RTL coding concepts. Soft Skills: Excellent communication skills with a strong motivation to learn, adapt, and collaborate effectively within cross-functional teams.