Junior Design Verification Engineer - Astera Labs

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field Strong understanding of Digital Logic and at least one programming language (C/C++ or Python) Basic familiarity with Verilog or SystemVerilog from academic projects or lab work A natural curiosity for "breaking things" and finding bugs, with a strong attention to detail Fluent in Hebrew and English with the ability to work effectively in a team environment

Verification Environment Development Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified Coverage & Quality Assurance Implement functional coverage models and analyze results to identify gaps in the verification process Drive designs toward 100% verification closure through comprehensive test development Contribute to verification methodology improvements and best practices Implement functional coverage models and analyze results to identify gaps in the verification process Drive designs toward 100% verification closure through comprehensive test development Contribute to verification methodology improvements and best practices Debug & Cross-Functional Collaboration Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle Apply analytical skills and debugging techniques to solve intricate verification challenges Collaborate effectively in a fast-paced, team-oriented R&D environment Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle Apply analytical skills and debugging techniques to solve intricate verification challenges Collaborate effectively in a fast-paced, team-oriented R&D environment

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field Strong understanding of Digital Logic and at least one programming language (C/C++ or Python) Basic familiarity with Verilog or SystemVerilog from academic projects or lab work A natural curiosity for "breaking things" and finding bugs, with a strong attention to detail Fluent in Hebrew and English with the ability to work effectively in a team environment