Junior Physical Design Engineer - Astera Labs

Bachelor’s degree in Electrical Engineering or a related technical field Foundational understanding of the RTL-to-GDS flow, with academic or internship exposure to areas such as floorplanning, placement, and routing Familiarity with advanced process technologies (e.g., 7nm and below) through coursework or hands-on projects Basic experience with signoff methodologies and tools, including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis Working knowledge of TCL or Python scripting for simple automation and support of EDA tool flows

Physical Implementation & Execution Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS) Own macro-level implementation with deep hands-on experience in floorplanning and complex routing Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS) Own macro-level implementation with deep hands-on experience in floorplanning and complex routing Signoff & Design Integrity Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR) Ensure first-pass silicon success through rigorous signoff flows and analysis Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR) Ensure first-pass silicon success through rigorous signoff flows and analysis Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness Methodology Development & Cross-Functional Collaboration Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity Leverage scripting and automation to make engineering environment faster and more robust Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity Leverage scripting and automation to make engineering environment faster and more robust

Bachelor’s degree in Electrical Engineering or a related technical field Foundational understanding of the RTL-to-GDS flow, with academic or internship exposure to areas such as floorplanning, placement, and routing Familiarity with advanced process technologies (e.g., 7nm and below) through coursework or hands-on projects Basic experience with signoff methodologies and tools, including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis Working knowledge of TCL or Python scripting for simple automation and support of EDA tool flows