Manager Design Verification - Astera Labs

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field 5+ years of digital design experience, including at least one full chip from spec to tapeout Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows Hands-on experience with timing closure, CDC, lint, and low-power design techniques Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration

RTL Design & Implementation Own RTL design for assigned blocks from microarchitecture through synthesis sign-off Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality Own RTL design for assigned blocks from microarchitecture through synthesis sign-off Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality Cross-Functional Execution Partner with architecture to translate specifications into implementation-ready microarchitecture Collaborate with verification on testplans, coverage closure, and bug triage Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure Partner with architecture to translate specifications into implementation-ready microarchitecture Collaborate with verification on testplans, coverage closure, and bug triage Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure Technical Leadership & Quality Mentor junior engineers and contribute to design methodology, scripts, and best practices Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments Drive structured, data-driven design decisions in support of aggressive tapeout schedules Mentor junior engineers and contribute to design methodology, scripts, and best practices Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments Drive structured, data-driven design decisions in support of aggressive tapeout schedules

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field 5+ years of digital design experience, including at least one full chip from spec to tapeout Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows Hands-on experience with timing closure, CDC, lint, and low-power design techniques Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration