Principal DFT Engineer - Astera Labs

Bachelor’s degree in Electrical Engineering or related technical field (Master’s preferred) 12+ years of experience in DFT design, implementation, and verification for complex ASIC/SoC designs Proven experience in leading DFT activities across full chip development cycles Deep expertise in DFT techniques including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG Strong understanding of DFT and Physical Design flows, including timing implications and integration challenges Experience with industry-standard DFT tools (Siemens Tessent, Synopsys TestMAX or equivalent) Solid experience with DFT verification methodologies and coverage analysis Strong scripting skills (Tcl, Python, or Perl) for automation and flow development

DFT Architecture & Technical Leadership Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies Lead DFT planning, specification, and quality tracking across the project lifecycle Provide technical leadership and drive DFT sign-off readiness to ensure successful tapeout

Bachelor’s degree in Electrical Engineering or related technical field (Master’s preferred) 12+ years of experience in DFT design, implementation, and verification for complex ASIC/SoC designs Proven experience in leading DFT activities across full chip development cycles Deep expertise in DFT techniques including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG Strong understanding of DFT and Physical Design flows, including timing implications and integration challenges Experience with industry-standard DFT tools (Siemens Tessent, Synopsys TestMAX or equivalent) Solid experience with DFT verification methodologies and coverage analysis Strong scripting skills (Tcl, Python, or Perl) for automation and flow development