Staff/ Principal Architect - Astera Labs

10+ years of experience in semiconductor architecture, ASIC design, or system engineering Strong expertise in PCIe architecture (Gen4/5/6+) and its ecosystem Deep understanding of Networking and Ethernet (e.g., 25G/50G/100G/400G and beyond) Experience designing high-speed, low-latency data paths Solid understanding of SoC architecture and integration challenges Experience working across full chip development lifecycle Strong analytical and problem-solving skills with ability to evaluate complex tradeoffs Ability to influence and collaborate across multiple engineering domains

Define and drive system and chip-level architecture for high-speed connectivity products Lead architecture for PCIe-based interconnects , networking protocols, and Ethernet subsystems Analyze system requirements and translate them into scalable and efficient hardware architectures Drive tradeoff analysis across performance, power, latency, area, and cost Collaborate with cross-functional teams including RTL, Physical Design, Firmware, Validation, and Product Engineering Define and review micro-architecture specifications and ensure alignment across teams Contribute to standard-based and custom protocols for next-generation AI infrastructure Support performance modeling, simulation, and architectural validation Work closely with customers and partners to understand emerging use cases and requirements Mentor engineers and help build strong technical leadership within the Israel R&D center

10+ years of experience in semiconductor architecture, ASIC design, or system engineering Strong expertise in PCIe architecture (Gen4/5/6+) and its ecosystem Deep understanding of Networking and Ethernet (e.g., 25G/50G/100G/400G and beyond) Experience designing high-speed, low-latency data paths Solid understanding of SoC architecture and integration challenges Experience working across full chip development lifecycle Strong analytical and problem-solving skills with ability to evaluate complex tradeoffs Ability to influence and collaborate across multiple engineering domains