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Staff/ Principal Physical Design Engineer - SoC EMIR Expert - Astera Labs

  • חברה: Astera Labs
  • מיקום: Israel
  • טכנולוגיות: Electrical Engineering

תיאור המשרה

Bachelor's or Master's degree in Electrical Engineering or a related technical field 10+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus) Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm) Deep understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture Ability to define and own EMIR methodologies Capability to identify issues early in the project lifecycle (preferably with experience in sub-N5 TSMC technologies) Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM Thermal analysis, self-heat and Statistical EM proficiency

תחומי אחריות

Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip Collaborate closely with Physical Design team to insure a full power integrity Be responsible on IR architecture for timing convergence Partner with Package Design engineers to perform Chip-Package co-analysis (CPM) Understand root-cause analysis for voltage drop violations and EM risks Be responsible and go-to person for any IR related issues

דרישות

Bachelor's or Master's degree in Electrical Engineering or a related technical field 10+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus) Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm) Deep understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture Ability to define and own EMIR methodologies Capability to identify issues early in the project lifecycle (preferably with experience in sub-N5 TSMC technologies) Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM Thermal analysis, self-heat and Statistical EM proficiency