Senior Hardware Design Engineer - Arago

Extensive experience in RTL design (Verilog/SystemVerilog) for control logic, datapaths, memory subsystems, and specialized processing units. Strong understanding of digital architecture, including pipelining, arbitration, memory hierarchy, and system-level integration. Proficiency in functional verification, including testbench development, assertions, coverage metrics, and debugging (UVM experience is a plus). Familiarity with ASIC and FPGA design flows, including synthesis, timing closure, and DFT. Comfortable working across the full hardware stack — from architectural specification and microarchitecture to physical implementation support. Language: English at a proficient level. French is a plus.

Do great things:we deliver work we’re proud to sign our name to. High velocity:speed matters. We move quickly, one step at a time. One unit:we’re all in this together, with relationships grounded in trust, respect, and camaraderie. Design, implement, and verify RTL blocks for memory, control, and compute subsystems within Arago’s custom multiphysics computation unit. Collaborate with Arago’s system software and architecture teams to define block-level specifications and ensure alignment with performance and integration goals. Develop and maintain functional verification infrastructure to validate design correctness across simulation and hardware testbenches. Support synthesis, timing analysis, and backend integration, working closely with Arago’s physical design and CAD engineers. Contribute to architectural exploration and hardware-software co-design efforts to shape future iterations of Arago’s compute platform. Extensive experience in RTL design (Verilog/SystemVerilog) for control logic, datapaths, memory subsystems, and specialized processing units. Strong understanding of digital architecture, including pipelining, arbitration, memory hierarchy, and system-level integration. Proficiency in functional verification, including testbench development, assertions, coverage metrics, and debugging (UVM experience is a plus). Familiarity with ASIC and FPGA design flows, including synthesis, timing closure, and DFT. Comfortable working across the full hardware stack — from architectural specification and microarchitecture to physical implementation support. Language: English at a proficient level. French is a plus. Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions. Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers). Relocation bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location. Healthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays. Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive. Reimbursement of 50% of the public transport subscription fee. A high-paced, multicultural (with 9 nationalities), and engineering-led environment.

Extensive experience in RTL design (Verilog/SystemVerilog) for control logic, datapaths, memory subsystems, and specialized processing units. Strong understanding of digital architecture, including pipelining, arbitration, memory hierarchy, and system-level integration. Proficiency in functional verification, including testbench development, assertions, coverage metrics, and debugging (UVM experience is a plus). Familiarity with ASIC and FPGA design flows, including synthesis, timing closure, and DFT. Comfortable working across the full hardware stack — from architectural specification and microarchitecture to physical implementation support. Language: English at a proficient level. French is a plus.