Senior Mixed-Signal Verification Engineer - Arago

Strong hands-on experience in ASIC or SoC verification. Experience verifying mixed-signal blocks or digital-to-analog and analog-to-digital interfaces. Strong SystemVerilog skills and practical experience with UVM or an equivalent verification methodology. Experience building verification environments and developing tests, assertions, scoreboards, and functional coverage. Good understanding of both digital design fundamentals and basic analog/mixed-signal concepts. Strong debugging skills, including the ability to investigate issues spanning RTL, models, clocks, resets, configuration, and analog behavior. Experience with scripting and automation, preferably Python, Tcl, shell, or similar. Language: English at a proficient level.

Strong hands-on experience in ASIC or SoC verification. Experience verifying mixed-signal blocks or digital-to-analog and analog-to-digital interfaces. Strong SystemVerilog skills and practical experience with UVM or an equivalent verification methodology. Experience building verification environments and developing tests, assertions, scoreboards, and functional coverage. Good understanding of both digital design fundamentals and basic analog/mixed-signal concepts. Strong debugging skills, including the ability to investigate issues spanning RTL, models, clocks, resets, configuration, and analog behavior. Experience with scripting and automation, preferably Python, Tcl, shell, or similar. Language: English at a proficient level. Own the mixed-signal verification methodology and verification plan for digital-to-analog interfaces on Arago SoCs. Build and maintain verification environments at block, subsystem, and SoC level. Develop tests, assertions, checkers, scoreboards, and functional coverage. Verify digital control and configuration of analog/mixed-signal circuitry across normal operation, corner cases, and error conditions. Run regressions, analyze coverage, debug failures, and drive verification to sign-off. Develop or integrate behavioral and real-number models needed for efficient mixed-signal simulation. Work closely with analog, RTL, architecture, firmware, and SoC verification teams to identify and resolve interface issues. Verification experience with complex high-speed interface IP such as PCIe, DDR/LPDDR, UCIe, SerDes, USB, CXL, or similar PHY-based interfaces. Experience verifying interface initialization, link training, calibration, adaptation, clocking, power-state transitions, or other digital/analog control loops. Experience with real-number modeling, SystemVerilog RNM, wreal, Verilog-AMS, or equivalent mixed-signal verification techniques. Experience developing or integrating behavioral models of analog/PHY components into digital verification environments. Experience with SoC-level integration and verification of complex interface IP. Experience with low-power verification, power-state management, or UPF. Experience driving a complex IP or SoC verification effort through coverage closure and tape-out. Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions. Meaningful stock option plan offered (included in the majority of full time offers). Healthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays. Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive.

Strong hands-on experience in ASIC or SoC verification. Experience verifying mixed-signal blocks or digital-to-analog and analog-to-digital interfaces. Strong SystemVerilog skills and practical experience with UVM or an equivalent verification methodology. Experience building verification environments and developing tests, assertions, scoreboards, and functional coverage. Good understanding of both digital design fundamentals and basic analog/mixed-signal concepts. Strong debugging skills, including the ability to investigate issues spanning RTL, models, clocks, resets, configuration, and analog behavior. Experience with scripting and automation, preferably Python, Tcl, shell, or similar. Language: English at a proficient level.